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power management 4a,f2.2mhzfsynchronousfstep-downfregulatorf withf15fpresetfoutputfvoltages sc187 features input voltage range 2.9 to 5.5v output voltage range 0.8v to 3.3v output current up to 4a ultra-small footprint <1 mm height solution minimum 1.8mhz switching frequency with no am radio band interference efciency up to 95% low output noise across load range excellent transient response start up into pre-bias output duty-cycle low dropout operation 100% shutdown current <1a externally programmable soft start time power good indicator input under-voltage lockout output over-voltage, current limit protection over-temperature protection thermally enhanced 3 x 3 x 0.6 (mm) mlpq-ut16 package temperature range -40 to +85c lead-free, halogen free, and rohs/weee compliant applications automotive power supplies routers and network cards lcd tv ofce automation ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the sc187 is a 4a synchronous step-down regulator designed to operate with an input voltage range of 2.9v to 5.5v. the device ofers ffteen pre-determined output voltages via four control pins programmable from 0.8 to 3.3 volts. the control pins allow for on-the-fly voltage changes, enabling system designers to implement dynamic power savings. the device is also capable of adjusting output voltage via an external resistor divider. the sc187 operates in pwm mode with fixed 2.2mhz oscillator frequency, allowing the use of small surface mount external components. connecting the control pins to logic low forces the device into shutdown mode reducing the supply current to less than 1a. connecting any of the control pins to logic high enables the converter and sets the output voltage accord - ing to table 1. other features include under-voltage lockout, programmable soft-start to limit in-rush current, power good indicator, over-temperature protection, and output short circuit protection. the sc187 is available in a thermally-enhanced, 3 x 3 x 0.6 (mm) mlpq-ut16 package. typical application circuit ctl 0 ctl 1 pgnd avin c in 22 f v in c out 47 f lx vout sc 187 r avin 1 pvin ctl 2 agnd ctl 3 ctl 0 ctl 1 ctl 2 ctl 3 l 1 . 0 h v out r pgood 100 k pgood c ss 10 nf ss c avin 10 nf rev 2.0 1
sc187 187 yyww xxxx pin confguration ordering information device package sc187ultrt (1)(2) 3 x 3 x 0.6 (mm) mlpq-ut16 SC187EVB (2) evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) device is lead-free, halogen free, and rohs/weee compliant. top view 1 2 3 4 12 11 10 9 16 15 14 13 5 6 7 8 t ss pgnd pvin ctl 0 agnd avin pgnd vout c t l 1 c t l 2 c t l 3 p g o o d p v i n l x l x p g n d 3fxf3fxf0.6f(mm)fmlpq-ut16 ja f=f40c/w;ff jc f=f7c/w marking information tablef1fCfoutputfvoltagefsettings ctl3 ctl2 ctl1 ctl0 output voltage 0 0 0 0 shutdown 0 0 0 1 0.8 0 0 1 0 1.00 0 0 1 1 1.025 0 1 0 0 1.05 0 1 0 1 1.20 0 1 1 0 1.25 0 1 1 1 1.30 1 0 0 0 1.50 1 0 0 1 1.80 1 0 1 0 2.20 1 0 1 1 2.50 1 1 0 0 2.60 1 1 0 1 2.80 1 1 1 0 3.00 1 1 1 1 3.30 yywwf=fdatefcodef xxxxf=fsemtechflotfnumberf 2
sc187 electrical characteristics exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. operation outside of the parameters specifed in the electrical characteristics section is not recommended. notes: (1) due to parasitic board inductance, the transient lx pin voltage at the point of measurement may appear larger than that which exists on silicon. the device is designed to tolerate the short duration transient voltages that will appear on the lx pin due to the deadtime diode conduction, for inductor currents up to the current limit setting of the device. (2) tested according to jedec standard jesd22-a114-b. (3) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb with thermal vias under the exposed pad per jesd51 standards. unless specifed: pvin = avin = 5.0v, vout = 1.50v, c in = 22f, c out = 2 x 22f; l = 1.0h; -40c t j +125 c; unless otherwise noted typical values are t a = +25 c. parameter symbol conditions min typ max units under-voltage lockout uvlo rising avin, pvin=avin 2.70 2.80 2.90 v hysteresis 300 mv output voltage tolerance (1) v out pvin= avin= 2.9 to 5.5v; i out =1a -1.5 +1.5 % current limit i limit peak lx current 5.0 6.0 7.0 a supply current i q i out = 0a 12 ma shutdown current i shdn ctl3-0 = agnd 1 10 a high side switch resistance (2) r dson_p i lx = 100ma, t j = 25 c 50 m low side switch resistance (2) r dson_n i lx = -100ma, t j = 25 c 35 l x leakage current (2) i lk(lx) pvin= avin= 5.5v; lx= 0v; ctl3-0 = agnd 1 10 a pvin= avin= 5.5v; lx= 5.0v; ctl3-0 = agnd -20 -1 load regulation v load-reg pvin= avin= 5.0v, i out =800ma to 4a 0.3 % absolute maximum ratings pvin and avin supply voltages (v) . . . . . . . . . -0.3 to +6.0 lx (v) (1) . . . . . . . . . . . . . . . . . . . . . . -0.3 to pvin +0.3v, 6v max vout (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to avin + 0.3 ctlx pins (v) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to avin + 0.3 vout short circuit duration . . . . . . . . . . . . . . . . continuous esd protection level (2) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 recommended operating conditions pvin and avin supply (v) . . . . . . . . . . . . . . . . . . 2.9 to +5.5 maximum output current (a) . . . . . . . . . . . . . . . . . . . . . . 4.0 input capacitor ( f ) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 output capacitor ( f ) . . . . . . . . . . . . . . . . . . . . . 47 or 2 x 22 output inductor ( h ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 thermal information thermal resistance, junction to ambient (3) (c/w) . . . . 40 thermal resistance, junction to case (c/w) . . . . . . . . . . 7 operating junction temperature (c) . . . . . . . -40 to +125 maximum junction temperature (c) . . . . . . . . . . . . . . +150 storage temperature range (c) . . . . . . . . . . . -65 to +150 peak ir refow temperature (10s to 30s) (c) . . . . . . +260 3
sc187 parameter symbol conditions min typ max units oscillator frequency f osc 1.8 2.2 2.6 mhz soft-start charging current (2) i ss +5 a foldback holding current i cl_hold average lx current 1 a impedence of pgood low r pgood_lo 10 pgood threshold v pg_th vout rising 90 % pgood delay v pg_dly asserted 2 ms pgood= low 20 s ctl x delay t en_dly from ctl x input high to ss starts rising 50 s ctl x input current (2) i ctlx ctl x =avin or agnd -2.0 2.0 a ctl x input high threshold v ctlx_hi 1.2 v ctl x input low threshold v ctlx_lo 0.4 v v out over voltage protection v ovp 110 115 120 % thermal shutdown temperature t sd 160 c thermal shutdown hysteresis t sd_hys 10 c notes: (1) the output voltage tolerance includes output voltage accuracy, voltage drift over temperature and the line regulation. (2) a negative current means the current fows into the pin and a positive current means the current fows out from the pin. electrical characteristics (continued) 4
sc187 pin descriptions pin # pin name pin function 1, 16 pvin input supply voltage for the converter power stage 2 agnd ground connection for the internal circuitry agnd needs to be connected to pgnd directly. 3 avin power supply for the internal circuitry avin is required to be connected to pvin through an r-c flter of 1 and 10nf. 4, 5, 6, 7 ctlx control bit see table 1 for decoding. these pins have 500k internal pull-down resistors which are switched in circuit whenever ctlx is low or when the part is in under-voltage lockout. 8 pgood power good indicator when the output voltage reaches the pgood threshold, this pin will be open-drain (after the pgood delay), otherwise, it is pulled low internally. 9 ss soft start connect a soft-start capacitor to program the soft start time. there is a 5a charging current fowing out of the pin. 10 vout output voltage sense pin 11,12,13 pgnd ground connection for converter power stage 14,15 lx switching node connect an inductor between this pin and the output capacitor. t thermal pad thermal pad for heat sinking purposes recommend to connect to pgnd. it is not connected internally. 5
sc187 block diagram control logic plimit amp current amp pwm comp error amp 500 mv ref ctl 1 ctl 2 ctl 3 vout p gnd l x p v in voltage select a v in a gnd oscillator and slope generator ctl 0 10 notes : a = pins 14 , 15 b = pins 11 , 12 , 13 c = 1 , 16 4 5 6 7 3 c a b 2 9 ss pgood detector delay 8 pgood 6
tbd sc187 typical characteristics efciency circuit conditions: c in = 22f/6.3v, c out = 2 x 22f/6.3v, c ss = 10nf. unless otherwise noted, l = 1.0h (toko: fdv0530s-1r0). r ds(on) fvariationfvs.finputfvoltage r ds(on) fvariationfvs.ftemperature - 10 - 5 0 5 10 15 20 25 30 35 2 . 5 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 input voltage ( v ) i lx = 100 ma , t a = 25 c v a r i a t i o n ( % ) n - channel p - channel - 20 - 15 - 10 - 5 0 5 10 15 20 - 40 - 15 10 35 60 85 n - channel p - channel i lx = 100 ma , t a = 25 c v a r i a t i o n ( % ) ambient temperature ( c ) totalflossf loadfregulationf -0.5% -0.4% -0.3% -0.2% -0.1% 0.0% 0.1% 0.2% 0.3% 0.4% 0.5% 0 0.5 1 1.5 2 2.5 3 3.5 4 output current(a) load regulation vin=5v,vout=3.3v vin=5v,vout=1.5v vin=3.3v,vout=1.5v t a = 25 c 60 65 70 75 80 85 90 95 100 0 1 2 3 4 output current(a) efficiency (%) vin=5v,vout=3.3v vin=5v,vout=1.5v vin=3.3v,vout=1.5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 3 3.5 4 output current(a) power loss(w) vin=5v,vout=3.3v vin=5v,vout=1.5v vin=3.3v,vout=1.5v 7
sc187 voutfripplef(vin=5v,fv out =1.5v)f@0afload voutfripple f(vin=3.3v,fv out =1.5v)@f0afload voutfripplef(vin=5v,fv out =1.5v)f@ffullfload voutfripplef(vin=3.3v,fv out =1.5v)f@ffullfload typical characteristics (continued) circuit conditions: c in = 22f/6.3v, c out = 2 x 22f/6.3v, c ss = 10nf. unless otherwise noted, l = 1.0h (toko: fdv0530s-1r0). il (1a/div) v out (10mv/div) lx(1v/div) vin (2v/div) il (1a/div) v out (10mv/div) lx(1v/div) vin (2v/div) il (1a/div) v out (10mv/div) lx(1v/div) vin (2v/div) il (1a/div) v out (10mv/div) lx(1v/div) vin (2v/div) voutfripplef (vin=5v,fv outf =f3.3v)f@fnofload voutfripplef (vin=5v,fv outf =f3.3v)f@ffullfload il (1a/div) v out (10mv/div) lx(1v/div) vin (2v/div) il (1a/div) v out (10mv/div) lx(1v/div) vin (2v/div) 8
sc187 startfupf ( ctl x )f fnofload startfupff ( ctl x )f ffullfload typical characteristics (continued) circuit conditions: c in = 22f/6.3v, c out = 2 x 22f/6.3v, c ss = 10nf. unless otherwise noted, l = 1.0h (toko: fdv0530s-1r0). time (500n s?div) s?div) ?div) v out (1v/div) v ctlx (5v/div) i out (5v/div) v in = 5v, = i out = 4a; v out = 1.5v pgood (5v/div) v in = 5. 0v i ou t = 0a mode = hi ch1: v en ch2: i ou t ch3: v ou t ch4: pgood v in = 5. 0v i ou t = 0a mode = hi ch1: v en ch2: i ou t ch3: v ou t ch4: pgood startfupf ( ctl x )f fnofload startfupfintofpre-biasedfoutputf ( v out =1.5v) startfupfintofpre-biasedfoutputf ( v out =3.3v) time (500n s?div) s?div) ?div) v out (1v/div) v ctlx (5v/div) i out (5v/div) pgood (5v/div) time (500n s?div) s?div) ?div) v out (2v/div) v ctlx (5v/div) i out (5v/div) pgood (5v/div) time (500 s?div) s?div) ?div) v out (2v/div) v ctlx (5v/div) i out (5a/div) pgood (5v/div) v in = 5v, = i out = 0; v out = 3.3v startfupf ( ctl x )f ffullfload 9
sc187 startfupfintofoutputfshortfcircuit typical characteristics (continued) circuit conditions: c in = 22f/6.3v, c out = 2 x 22f/6.3v, c ss = 10nf. unless otherwise noted, l = 1.0h (toko: fdv0530s-1r0). time (500n s?div) s?div) ?div) v ss (1v/div) lx (5v/div) i lx (2a/div) v out (500mv/div) v in = 5v vidftransition fffullfload v out (200mv/div) i out (2a/div) time (100m s?div) s?div) ?div) v in = 5v; v out = 1.5v to 1.8v to 1.5v mode = hi ch 3 v ou t ch 1 v lx ch 2 i lx ch 4 pg ood ch 3 v ou t mode = hi ch 1 v lx ch 2 i lx ch 4 v in mode = hi ch 3 v ou t ch 1 v lx ch 2 i lx ch 4 pg ood ch 3 v ou t mode = hi ch 1 v lx ch 2 i lx ch 4 v in outputfshortfcircuitf recoveryffromfshortfcircuit v in = 5v; v out = 1.5v v in = 5v; v out = 1.5v outputfshortfcircuit recoveryffromfshortfcircuit v in = 5v; v out = 3.3v v in = 5v; v out = 3.3v 10
sc187 transientfresponsef ( v out =1.5v,fi step =2a) transientfresponsef ( v out =3.3v,fi step =2a) typical characteristics (continued) circuit conditions: c in = 22f/6.3v, c out = 2 x 22f/6.3v, c ss = 10nf. unless otherwise noted, l = 1.0h (toko: fdv0530s-1r0). time (20 s?div) s?div) ?div) v out (100mv/div) i out (1a/div) time (20 s?div) s?div) ?div) v out (100mv/div) i out (1a/div) v in = 5v; i out = 1a to 3a to 1a v in = 5v; i out = 1a to 3a to 1a 11
sc187 applications information detailed description the sc187 is a synchronous step-down pwm (pulse width modulated) dc-dc converter utilizing a 2.2mhz fxed-fre - quency voltage mode architecture. the device is designed to operate in fxed-frequency pwm mode. the switching frequency is chosen to minimize the size of the external inductor and capacitors while maintaining high efciency. operation during normal operation, the pmos mosfet is activated on each rising edge of the internal oscillator. the period is set by the onboard oscillator. the device has an internal synchronous nmos rectifier and does not require a schottky diode on the lx pin. the device operates as a buck converter in pwm mode with a fxed frequency of 2.2mhz. protection features the sc187 provides the following protection features: current limit over-voltage protection soft-start operation thermal shutdown current limit & ocp the internal pmos power device in the switching stage is protected by a current limit feature. if the inductor current is above the pmos current limit for 16 consecutive cycles, the part enters foldback current limit mode and the output current is limited to the current limit holding current (i cl_hold ) which is approximately 1a. under this condition, the output voltage will be the product of i cl_hold and the load resistance. the sc187 is capable of sustaining an indefnite short circuit without damage. during the soft start, if current limit has occurred before the ss voltage has reached 400mv, the part enters foldback current limit mode. foldback current limit mode will be disabled during soft-start after the ss voltage is higher than 400mv. over-voltage protection in the event of a 15% over-voltage on the output, the pwm drive is disabled with the lx pin foating. switching ? ? ? ? does not resume until the output voltage falls below the nominal v out regulation voltage. programmable output voltage the sc187 has fifteen pre-determined output voltage values which can be individually selected by program - ming the ctl input pins (see table 1 output voltage settings). each ctl pin has an active 500k internal pull - down resistor. the 500k resistor is switched in circuit whenever the ctl input voltage is below the input thresh- old, or when the part is in under voltage lockout. it is recommended to tie all high ctl pins together and use an external pull-up resistor to avin if there is no enable signal or if the enable input is an open drain/collector signal. the ctl pins may be driven by a microprocessor to allow dynamic voltage adjustment for systems that reduce the supply voltage when entering sleep states. avoid all zeros being present on the ctl pins when changing program - mable output voltages as this would disable the device. sc187 is also capable of regulating a diferent (higher) output voltage, which is not shown in the table 1, via an external resistor divider. there will be a typical 2a current fowing into the vout pin. the typical schematic for an adjustable output voltage option from the standard 1.0v with ctlx=[0010], is shown in figure 2. rfb1 and rfb2 are used to adjust the desired output voltage. if the rfb2 current is such that the 2a vout pin current can be ignored, then rfb1 can be found using the next equation. rfb2 needs to be low enough in value for the current through the resistor chain to be at least 20a in order to ignore the vout pin current. ctl 0 ctl 1 pgnd avin lx vout sc 187 pvin ctl 2 agnd ctl 3 pgood ssa c ss 10 nf v out c out l r fb 2 10 k c ff r fb 1 r fb 1 = ( v out - 1 ) x r fb 2 for ctl x = 0010 ( 1 . 0 v ) v in c avin 10 nf r avin - 1 c in 22 f r pgood 100 k enable figuref1ffoutputfvoltagefprogramming 12
sc187 applications information (continued) 2 fb ostd ostd out 1 fb r v v v r u where v ostd is the pre-determined output voltage via the ctl pins. c ff is needed to maintain good transient response perfor - mance. the correct value of c ff can be found using the following equation. ) 5 . 0 v v ( v v ] k [ r 5 . 0 v 5 . 2 ] nf [ c ostd ostd ostd out 1 fb 2 out ff u u : u to simplify the design, it is recommended to program the desired output voltage from a standard 1.0v as shown in figure 2 with a proper c ff calculated from equation 2. for programming the output voltage from other standard voltages, r fb1 , r fb2 and c ff need to be adjusted to conform to the previous equations. shut down when all ctl pins are low, the device will run in shutdown mode, drawing less than 1a from the input power supply. the internal switches and band-gap voltage will be imme - diately turned of. thermal shutdown the device has a thermal shutdown feature to protect the sc187 if the junction temperature exceeds 160c. during thermal shutdown, the on-chip power devices are dis - abled, floating the lx output. when the temperature drops by 10c, it will initiate a soft start cycle to resume normal operation. under-voltage lockout under-voltage lockout (uvlo) is enabled when the input voltage drops below the uvlo threshold. this prevents the device from entering an ambiguous state in which regulation cannot be maintained. hysteresis of approxi - mately 300mv is included to prevent chattering near the threshold. when the avin voltage rises back to the turn- on threshold and ctl x is high, the soft-start mode is resumed. power good the power good (pgood) is an open-drain output. when the output voltage drops below 10% of nominal voltage, the pgood pin is pulled low after a 20s delay. during start-up, pgood will be asserted 2ms (typ.) after the output voltage reaches 90% of the fnal regulation voltage. the faults of over voltage, fold-back current limit mode and thermal shutdown will force pgood low after a 20 s delay. when recovering from a fault, pgood will be asserted 1.8ms (typ.) after vout reaches 90% of the fnal regulation voltage. soft-start the soft-start mode is activated after avin reaches its uvlo voltage threshold and ctl x is set high to enable the part. a thermal shutdown event will also activate the soft start sequence. the soft-start mode controls the slew-rate of the output voltage during start-up thus limiting in-rush current on the input supply. during start-up, the reference voltage for the error amplifer is clamped by the voltage on the ss pin. the output voltage slew rate during soft- start is determined by the value of the external capacitor connected to the ss pin and the internal 5a charging current. the device requires a minimum soft-start time from enable to final regulation in the order of 200s, including the 50s enable delay. as a result the soft start capacitor, css, should be higher than 1.5nf. 100% duty-cycle operation sc187 is capable of operating at 100% duty-cycle. when the difference between the input voltage and output voltage is less than the minimum dropout voltage, the pmos switch is completely on, operating in 100% duty- cycle. the minimum dropout voltage is the output current multiplied by the on-resistance of the internal pmos switch and the dc-resistance of the inductor when pmos switch is on continuously. 13
sc187 output l-c flter selection sc187 has fxed internal loop-gain compensation. it is optimized for x5r or x7r ceramic output capacitors and an output l-c flter corner frequency of less than 34khz. the output l-c corner frequency can be determined by equation 2. out c c l 2 1 f u s in general, the inductor is chosen to set the inductor ripple current to approximately 30% of the maximum output current. it is recommended to use a typical inductor value of 1h to 2.2h with output ceramic capacitors of 44f or higher capacitance. lower inductance should be consid - ered in applications where faster transient response is required. more output capacitance will reduce the output deviation for a particular load transient. when using low inductance, the maximum peak inductor current at any condition (normal operation and start up) can not exceed 5a which is the guaranteed minimum current limit. the saturation current rating of the inductor needs to be at least larger than the peak inductor current which is the maximum output current plus half of inductor ripple current. applications information (continued) 14
sc187 figuref2ffrecommendedfpcbflayoutf(topflayer) figuref3ffbottomflayerfdetail pcb layout considerations the layout diagram in figure 2 shows a recommended top-layer pcb for the sc187 and supporting components. figure 3 shows the bottom layer for this pcb. fundamental layout rules must be followed since the layout is critical for achieving the performance specified in the electrical characteristics table. poor layout can degrade the perfor - mance of the dc-dc converter and can contribute to emi problems, ground bounce, and resistive voltage losses. poor regulation and instability can result. the following guidelines are recommended when devel - oping a pcb layout: the input capacitor, c in should be placed as close to the pvin and pgnd pins as possible. this capacitor provides a low impedance loop for the pulsed currents present at the buck converters input. use short wide traces to connect as closely to the ic as possible. this will minimize emi and input voltage ripple by localizing the high frequency current pulses. keep the lx pin traces as short as possible to minimize pickup of high frequency switching edges to other parts of the circuit. c out and l should be connected as close as possible between the lx and pgnd pins, with a direct return to the pgnd pin from c out . route the output voltage feedback/sense path away from the inductor and lx node to minimize noise and magnetic interference. use a ground plane referenced to the sc187 pgnd pin. use several vias to connect to the component side ground to further reduce noise and interference on sensitive circuit nodes. if possible, minimize the resistance from the vout and pgnd pins to the load. this will reduce the voltage drop on the ground plane and improve the load regulation. and it will also improve the overall efciency by reducing the copper losses on the output and ground planes. 1. 2. 3. 4. 5. applications information (continued) 15
sc187 outline drawing C 3x3 mlpq-ut16 land pattern C 3x3 mlpq-ut16 .114 .118 3.00 .122 2.90 3.10 notes: bbb c a b aaa c .003 .061 16 .067 .000 .020 - - (.006) 0.08 16 .071 1.55 .024 .002 0.00 0.50 1.80 1.70 0.05 0.60 (0.152) - - .004 0.10 1.55 2.90 1.70 1.80 3.00 3.10 0.50 bsc .020 bsc 0.30 .012 .020 .016 0.40 0.50 .122 .118 .114 .071 .067 .061 a coplanarity applies to the exposed pad as well as the terminals. 2. controlling dimensions are in millimeters (angles in degrees). 1. inches dimensions nom e bbb aaa a1 a2 d1 e1 dim n l e min d a millimeters max min max nom e b d e/2 e bxn 1 2 n pin 1 indicator (laser mark) a1 c seating plane lxn e/2 d/2 b .007 .009 .012 0.18 0.23 0.30 3. dap is 1.90 x 1.90mm. d1 e1 a2 a 1. controlling dimensions are in millimeters (angles in degrees). k c z p y x g h .146 .020 .012 .031 .083 .067 3.70 0.30 0.80 0.50 1.70 2.10 dim (2.90) millimeters dimensions (.114) inches k .067 1.70 failure to do so may compromise the thermal and/or functional performance of the device. shall be connected to a system ground plane. thermal vias in the land pattern of the exposed pad 3. p x h (c) r r .006 0.15 y g z this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 2. 16
semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com contact information sc187 ? semtech 2011 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specifed maximum ratings or operation outside the specifed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. inclusion of semtech products in such ap - plications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its ofcers, em - ployees, subsidiaries, afliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. 17

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